1. Field of the Invention
The present invention relates generally to a method of manufacturing semiconductor devices, and more particularly, to a method for forming Complementary Metal-Oxide-Semiconductor (CMOS) devices having ultra-shallow junctions.
2. Description of the Prior Art
As semiconductor devices, such as Complementary Metal-Oxide-Semiconductor devices, become highly integrated, the area occupied by the devices shrinks, as well as the design rule. With advances in semiconductor technology, the dimensions of the integrated circuit (IC) devices have shrunk to the deep sub-micron range. As the semiconductor device continuously shrinks to deep sub-micron region, some problems are incurred due to the process of scaling down.
A cross-sectional view of a fabricating shallow junctions process in Complementary Metal-Oxide-Semiconductor device of the prior art is illustrated in FIG. 1A to FIG. 1E. A semiconductor substrate 2 having an n-well region 4, a p-well region 6, and a shallow trench isolation (STI) 8 region is provided. Poly-gates 10 are also formed over the n-well region 4 and the p-well region 6 respectively, as shown in FIG. 1A. First, amorphous regions 12 and 13 are formed on the n-well region 4 and the p-well region 6 of the foresaid structure using the Ge Pre-amorphization method 9 with energy of between 2 keV and 5 keV. A photoresist layer 14 is formed over the p-well region 6, and then the p-type ion implantation 16 is carried out to dope a part of the diffusion source layer forming p-type shallow junctions 18 over the n-well region 4, by using boron ions with energy less then 1 keV, as shown in FIG. 1B. Therefore, the diffusion layer formed over the n-well region 4 contains p-type ions. After removing the photoresist layer 14, another photoresist layer 20 is formed over the n-well region 4 serving as an ion implantation mask, and then n-type ion implantation 22 is carried out to dope a part of the diffusion source layer formed n-type shallow junctions 24 over the p-well region 6, by using arsenic ions with energy less then 2 keV, as shown in FIG. 1C. Therefore, the diffusion layer formed over the p-well region 6 contains n-type ions. Next, the spacers 26 are formed on the sidewall of poly-gate by depositing and etching back after removing the photoresist layer 20, and the result is depicted in FIG. 1D. Then, the p-type ion implantation 16 and the n-type ion implantation 22 are carried out to the n-well region 4 and the p-well region 6 respectively again. Finally, one step rapid thermal process (RTP) at about 1000.degree. C. for about 15 seconds is carried out to form the source/drain regions 28 and 30 in the Complementary Metal-Oxide-Semiconductor devices, as shown in FIG. 1E.
The evolution of integrated circuits has involved scaling down the device geometries. In deep sub-micron Complementary Metal-Oxide-Semiconductor technology, shallow junctions are required to alleviate or avoid the influences of the short channel effect. As the channel length of the Complementary Metal-Oxide-Semiconductor is scaled, it has become necessary to reduce the source/drain(S/D)junctions depths (in the drain extension regions near the channel) to prevent short channel effects. And yet, the conventional shallow junctions process is very difficult to perform below 0.18 micrometer. However, the formation of p+/n source/drain shallow junctions using boron ions implants and n+/p source/drain shallow junctions using arsenic ions or phosphorous ions implants face severe physical limitations. The influence of ion channel effect on boron ions is greater than that of arsenic, because the diffusion coefficient of boron ions is greater than that of arsenic ions or phosphorous ions. Therefore, forming the ultra-shallow junction p+/n source/drain and n+/p source/drain simultaneously are very difficult.
According to the channel effect of ion implantation, this will lead to difficulty with junction depth control after ions implant in the semiconductor device. Hence, in the conventional process, the Pre-amorphization by a germanium (Ge) implant prior to the dopant implant eliminates ion-channeling completely. The Ge Pre-amorphization implantation creates an amorphous layer in the crystalline substrate. However, it also creates defects (interstitials) beyond the amorphous layer/crystalline substrate interface. Moreover, the Ge Pre-amorphization implantation will cause damage on the silicon substrate surface.
Conventionally, the ion implant energy, which reduced the projected range of the dopants, has to be reduced to reduce the junctions depth. For low energy of the boron ions implants (less than 10keV), it is not possible to reduce the junctions depth eminently by reducing the energy of the ion implant. Transient enhance diffusion(TED)results from the boron dopant combining with interstitials in the silicon. The boron-interstitial combination diffuses much faster during the annealing period than the boron alone causing deeper junctions depths. Even though shallow junctions process is performed by boron ion implants energy below sub-keV (less than 1 keV), the TED and OED (Oxygen enhance diffusion) effects are still existing and throughput is very less too. Moreover, boron ion implants energy below sub-keV is not very practical using today's equipment, and the ion implanter apparatus not only must change the new one but also is not a suited one to mass production up to the present.
In accordance with the above description, a new and improved method for fabricating the Complementary Metal-Oxide-Semiconductor device is therefore necessary, so as to raise the yield and quality of the follow-up process.